1. Field of the Invention
This invention relates to an integrated circuit in which a high-speed access device and a low-speed access device are connected by a common bus, and to a method of controlling this integrated circuit.
2. Description of the Related Art
When a digital circuit is constructed, a plurality of devices are connected to a single common bus. Transfer of data to the plurality of devices is performed through the single common bus.
It is necessary to raise the frequency of the operating clock pulses in order to raise the data transfer speed. Owing to the effects of bus capacitative load, however, there is an upper limit on the frequency of the operating clock pulses. Though changing the material used in the bus in order to improve the bus characteristic is conceivable, this would raise cost. Further, if the frequency of the operating clock pulses is raised to achieve high speed, operation will not be stable in a circuit having a long bus.